With the continuous development of the semiconductor technology, the technical node of the semiconductor processes has become smaller and smaller by following the Moore's law. In order to match the requirements for decreasing the technical node, the channel length of MOSFETs has been continuously decreased. Decreasing the channel length of MOSFETs may bring some advantages, such as increasing the integration level, and increasing the switch speed of the MOSFETs, etc.
However, with the decreasing of the channel length of the semiconductor devices, the distance between the source regions of the semiconductor devices and the drain regions of the semiconductor devices is also correspondingly decreased. Thus, the control ability of the gate structures of the semiconductor devices to the channel regions become worse. That is, the pinch off of the channel regions of the semiconductor devices has become more and more difficult. Thus, the subthreshold leakage may be easy to happen. The subthreshold leakage is also referred as the short channel effects (SCEs).
In order to better match the requirements for device miniaturization, the semiconductor process has been gradually transferred from the planar MOSFETs to more efficient three-dimensional transistors, such as fin field-effect transistors (FinFETs), etc. In a FinFET, the gate structure is able to control the fin structure from two sides of the fin. Thus, comparing with a planar MOSFET, the control ability of the gate structure to the channel region may be stronger; and the SCEs may be effectively controlled. Further, comparing with other device structures, FinFETs may have a better compatibility with the existing manufacturing technology of integrated circuits.
With the continuous development of the semiconductor technology, the carrier mobility enhancement technology has attracted extensive research and applications in FinFETs. Increasing the carrier mobility of the channel regions of the FinFETs is able to increase the drive current of the FinFETs. Thus, the performance of the FinFETs may be improved.
Embedded silicon germanium (e-SiGe) method is one of the several approaches for increasing the carrier mobility of channel regions of the FinFETs. The SiGe structures embedded in the fins, or on the fins of the FinFETs are able to induce a compressive stress or a tensile stress in the channel regions of the FinFETS because of the crystal lattice mismatch between the substrate and the embedded SiGe structures. In a semiconductor device, a compressive stress or a tensile stress is able to change the bandgap and/or carrier mobility of the channel region. Thus, improving the performance of the FinFETs by the e-SiGe method has become a more and more common method. Specifically, by properly controlling the compressive stress or the tensile stress applied on channel regions of the FinFETs by the embedded SiGe structures, the carrier mobility of the channel regions of the FinFETs is increased. Thus, the drive current of the FinFETs is increased; and the performance of the FinFETs is enhanced. The carriers in NMOS FinFETs are electrons; and the carriers in PMOS FinFETs are holes.
However, the quality of embedded SiGe structures, are also referred as a stress layer, i.e., material layers applying the compressive stress or tensile stress to the channel regions of the FinFETs, formed by existing methods may not match desired requirements. Thus, the electrical properties of the FinFETs having such a stress layer may not match requirements neither. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.